MC9S12G Datasheet, PDF (120/1160 Pages) Freescale Semiconductor, Inc – Ignores external trigger. Performs one conversion sequence and stops.

Port Integration Module (S12GPIMV0)
The family devices share same sets of package options (refer to device overview section) determining the
availability of pins and the related PIM memory maps. The corresponding devices are referenced
throughout this section by their group name as shown in Table 2-2.
Table 2-2. Device Groups
Group
Devices with same set of package options
G1 S12G240, S12GA240, S12G192, S12GA192, S12G128, S12G96
G2 S12G64, S12G48, S12GN48
G3 S12GN32, S12GN16
2.1.3 Features
The PIM includes these distinctive registers:
• Data registers and data direction registers for ports A, B, C, D, E, T, S, M, P, J and AD when used
as general-purpose I/O
• Control registers to enable/disable pull devices and select pullups/pulldowns on ports T, S, M, P, J
and AD on per-pin basis
• Single control register to enable/disable pull devices on ports A, B, C, D and E, on per-port basis
and on BKGD pin
• Control registers to enable/disable open-drain (wired-or) mode on ports S and M
• Interrupt flag register for pin interrupts on ports P, J and AD
• Control register to configure IRQ pin operation
• Routing register to support programmable signal redirection in 20 TSSOP only
• Routing register to support programmable signal redirection in 100 LQFP package only
• Package code register preset by factory related to package in use, writable once after reset. Also
includes bit to reprogram routing of API_EXTCLK in all packages.
• Control register for free-running clock outputs
•
A standard port pin has the following minimum features:
• Input/output selection
• 3.15 V - 5 V digital and analog input
• Input with selectable pullup or pulldown device
Optional features supported on dedicated pins:
• Open drain for wired-or connections
• Key-wakeup feature: External pin interrupt with glitch filtering, which can also be used for wakeup
from stop mode.
MC9S12G Family Reference Manual, Rev.1.01
120
Freescale Semiconductor
This document is valid for the S12G96 and the S12G128 device. All information related to other devices is preliminary.