MC9S12G Datasheet, PDF (1090/1160 Pages) Freescale Semiconductor, Inc – Ignores external trigger. Performs one conversion sequence and stops.

Electrical Characteristics
This constraint exists since the sample buffer amplifier can not drive beyond the power supply levels that
it ties to. If the input level goes outside of this range it will effectively be clipped.
Table A-14. ATD Operating Characteristics
Supply voltage 3.13 V < V_DDA < 5.5 V, -40^oC < T_J < 150^oC
Num C
Rating
Symbol
Min
Typ
Max
Unit
1 D Reference potential
Low
High
V_RL
V_SSA
—
V_DDA/2
V
V_RH
V_DDA/2
—
V_DDA
V
2 D Voltage difference V_DDX to V_DDA
∆_VDDX
–2.35
0
0.1
V
3 D Voltage difference V_SSX to V_SSA
4 C Differential reference voltage¹
∆_VSSX
–0.1
0
V_RH-V_RL
3.13
5.0
0.1
V
5.5
V
5 C ATD Clock Frequency (derived from bus clock via the
prescaler bus)
f_ATDCLk
0.25
8.0
MHz
ATD Conversion Period²
12 bit resolution:
8 D _{10 bit resolution:}
8 bit resolution:
N_CONV12
20
N_CONV10
19
N_CONV8
17
42
ATD
41
clock
39
Cycles
1 _{Full accuracy is not guaranteed when differential voltage is less than 4.50 V}
2 _{The minimum time assumes a sample time of 4 ATD clock cycles. The maximum time assumes a sample time of 24 ATD clock}
cycles and the discharge feature (SMP_DIS) enabled, which adds 2 ATD clock cycles.
A.3.2 Factors Influencing Accuracy
Source resistance, source capacitance and current injection have an influence on the accuracy of the ATD.
A further factor is that PortAD pins that are configured as output drivers switching.
A.3.2.1 Port AD Output Drivers Switching
PortAD output drivers switching can adversely affect the ATD accuracy whilst converting the analog
voltage on other PortAD pins because the output drivers are supplied from the VDDA/VSSA ATD supply
pins. Although internal design measures are implemented to minimize the affect of output driver noise, it
is recommended to configure PortAD pins as outputs only for low frequency, low load outputs. The impact
on ATD accuracy is load dependent and not specified. The values specified are valid under condition that
no PortAD output drivers switch during conversion.
A.3.2.2 Source Resistance
Due to the input pin leakage current as specified in conjunction with the source resistance there will be a
voltage drop from the signal source to the ATD input. The maximum source resistance R_S specifies results
in an error (10-bit resolution) of less than 1/2 LSB (2.5 mV) at the maximum leakage current. If device or
operating conditions are less than worst case or leakage-induced error is acceptable, larger values of source
resistance of up to 10Kohm are allowed.
MC9S12G Family Reference Manual, Rev.1.01
1090
Freescale Semiconductor
This document is valid for the S12G96 and the S12G128 device. All information related to other devices is preliminary.