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| MC9S12G Datasheet, PDF (568/1160 Pages) Freescale Semiconductor, Inc – Ignores external trigger. Performs one conversion sequence and stops. | |||
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Serial Communication Interface (S12SCIV5)
18.3.1 Module Memory Map and Register Deï¬nition
The memory map for the SCI module is given below in Figure 18-2. The address listed for each register is
the address offset. The total address for each register is the sum of the base address for the SCI module and
the address offset for each register.
18.3.2 Register Descriptions
This section consists of register descriptions in address order. Each description includes a standard register
diagram with an associated ï¬gure number. Writes to a reserved register locations do not have any effect
and reads of these locations return a zero. Details of register bit and ï¬eld function follow the register
diagrams, in bit order.
Register
Name
Bit 7
0x0000
R
SCIBDH1 W IREN
6
TNP1
5
TNP0
4
SBR12
3
SBR11
2
SBR10
1
SBR9
0x0001
R
SCIBDL1 W SBR7
SBR6
SBR5
SBR4
SBR3
SBR2
SBR1
0x0002
R
SCICR11
LOOPS
W
SCISWAI
RSRC
M
WAKE
ILT
PE
0x0000
R
0
0
0
0
SCIASR12
RXEDGIF
W
BERRV BERRIF
0x0001
R
0
0
0
0
0
SCIACR12
RXEDGIE
W
BERRIE
0x0002
R
0
0
0
0
0
SCIACR22 W
BERRM1 BERRM0
0x0003
R
SCICR2 W
TIE
TCIE
RIE
ILIE
TE
RE
RWU
0x0004
R TDRE
TC
RDRF
IDLE
OR
NF
FE
SCISR1 W
0x0005
R
0
SCISR2
AMAP
W
0
TXPOL
RXPOL
BRK13
TXDIR
= Unimplemented or Reserved
Figure 18-2. SCI Register Summary (Sheet 1 of 2)
Bit 0
SBR8
SBR0
PT
BKDIF
BKDIE
BKDFE
SBK
PF
RAF
MC9S12G Family Reference Manual, Rev.1.01
568
Freescale Semiconductor
This document is valid for the S12G96 and the S12G128 device. All information related to other devices is preliminary.
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