MC9S12G Datasheet, PDF (161/1160 Pages) Freescale Semiconductor, Inc – Ignores external trigger. Performs one conversion sequence and stops.

Port Integration Module (S12GPIMV0)
Global Address
Register Name
0x024C
PERS
Table 2-21. Block Register Map (G3) (continued)
Bit 7
R
PERS7
W
6
PERS6
5
PERS5
4
PERS4
3
PERS3
2
PERS2
1
PERS1
Bit 0
PERS0
0x024D
PPSS
R
PPSS7
W
PPSS6
PPSS5
PPSS4
PPSS3
PPSS2
PPSS1
PPSS0
0x024E
WOMS
R
WOMS7
W
WOMS6
WOMS5
WOMS4
WOMS3
WOMS2
WOMS1
WOMS0
0x024F
PRR0
R
PRR0P3 PRR0P2 PRR0T31 PRR0T30 PRR0T21 PRR0T20 PRR0S1 PRR0S0
W
0x0250
R
0
0
0
0
0
0
PTM
W
PTM1
PTM0
0x0251
R
0
0
0
0
0
0
PTIM1 PTIM0
PTIM
W
0x0252
R
0
0
0
0
0
0
DDRM
W
DDRM1 DDRM0
0x0253
R
0
0
0
0
0
0
0
0
Reserved
W
0x0254
R
0
0
0
0
0
0
PERM
W
PERM1 PERM0
0x0255
R
0
0
0
0
0
0
PPSM
W
PPSM1 PPSM0
0x0256
R
0
0
0
0
0
0
WOMM
W
WOMM1 WOMM0
0x0257
R
0
0
0
0
PKGCR
APICLKS7
W
PKGCR2 PKGCR1 PKGCR0
0x0258
PTP
R
0
W
0
PTP5
PTP4
PTP3
PTP2
PTP1
PTP0
0x0259
PTIP
R
0
W
0
PTIP5
PTIP4
PTIP3
PTIP2
PTIP1
PTIP0
0x025A
DDRP
R
0
W
0
DDRP5 DDRP4 DDRP3 DDRP2 DDRP1 DDRP0
= Unimplemented or Reserved
MC9S12G Family Reference Manual, Rev.1.01
Freescale Semiconductor
161
This document is valid for the S12G96 and the S12G128 device. All information related to other devices is preliminary.