MC9S12G Datasheet, PDF (500/1160 Pages) Freescale Semiconductor, Inc – Ignores external trigger. Performs one conversion sequence and stops.

Freescale’s Scalable Controller Area Network (S12MSCANV3)
Module Base + 0x000B
Access: User read/write¹
7
R
0
W
6
5
4
3
2
1
0
0
IDHIT2
IDHIT1
IDAM1
IDAM0
Reset:
0
0
0
0
0
0
0
= Unimplemented
Figure 16-15. MSCAN Identifier Acceptance Control Register (CANIDAC)
1 _{Read: Anytime}
Write: Anytime in initialization mode (INITRQ = 1 and INITAK = 1), except bits IDHITx, which are read-only
0
IDHIT0
0
Table 16-18. CANIDAC Register Field Descriptions
Field
Description
5-4
Identifier Acceptance Mode — The CPU sets these flags to define the identifier acceptance filter organization
IDAM[1:0] (see Section 16.4.3, “Identifier Acceptance Filter”). Table 16-19 summarizes the different settings. In filter closed
mode, no message is accepted such that the foreground buffer is never reloaded.
2-0
Identifier Acceptance Hit Indicator — The MSCAN sets these flags to indicate an identifier acceptance hit (see
IDHIT[2:0] Section 16.4.3, “Identifier Acceptance Filter”). Table 16-20 summarizes the different settings.
IDAM1
0
0
1
1
Table 16-19. Identifier Acceptance Mode Settings
IDAM0
0
1
0
1
Identifier Acceptance Mode
Two 32-bit acceptance filters
Four 16-bit acceptance filters
Eight 8-bit acceptance filters
Filter closed
Table 16-20. Identifier Acceptance Hit Indication
IDHIT2
0
0
0
0
1
1
1
1
IDHIT1
0
0
1
1
0
0
1
1
IDHIT0
0
1
0
1
0
1
0
1
Identifier Acceptance Hit
Filter 0 hit
Filter 1 hit
Filter 2 hit
Filter 3 hit
Filter 4 hit
Filter 5 hit
Filter 6 hit
Filter 7 hit
The IDHITx indicators are always related to the message in the foreground buffer (RxFG). When a
message gets shifted into the foreground buffer of the receiver FIFO the indicators are updated as well.
MC9S12G Family Reference Manual, Rev.1.01
500
Freescale Semiconductor
This document is valid for the S12G96 and the S12G128 device. All information related to other devices is preliminary.