MC9S12G Datasheet, PDF (345/1160 Pages) Freescale Semiconductor, Inc – Ignores external trigger. Performs one conversion sequence and stops.

S12 Clock, Reset and Power Management Unit (S12CPMU)
NOTE
Care should be taken to ensure that the bus frequency does not exceed the
specified maximum when frequency modulation is enabled.
Table 10-7. CPMUPLL Field Descriptions
Field
Description
5, 4
PLL Frequency Modulation Enable Bits — FM1 and FM0 enable frequency modulation on the VCOCLK. This
FM1, FM0 is to reduce noise emission. The modulation frequency is f_ref divided by 16. See Table 10-8 for coding.
Table 10-8. FM Amplitude selection
FM1
0
0
1
1
FM0
0
1
0
1
FM Amplitude /
f_VCO Variation
FM off
±1%
±2%
±4%
10.3.2.8 S12CPMU RTI Control Register (CPMURTI)
This register selects the time-out period for the Real Time Interrupt.
The clock source for the RTI is either IRCCLK or OSCCLK depending on the setting of the RTIOSCSEL
bit. In Stop Mode with PSTP=1 (Pseudo Stop Mode) and RTIOSCSEL=1 the RTI continues to run, else
the RTI counter halts in Stop Mode.
0x003B
R
W
Reset
7
RTDEC
0
Read: Anytime
Write: Anytime
6
RTR6
5
RTR5
4
RTR4
3
RTR3
2
RTR2
1
RTR1
0
0
0
0
0
0
Figure 10-11. S12CPMU RTI Control Register (CPMURTI)
0
RTR0
0
MC9S12G Family Reference Manual, Rev.1.01
Freescale Semiconductor
345
This document is valid for the S12G96 and the S12G128 device. All information related to other devices is preliminary.