MC9S12G Datasheet, PDF (145/1160 Pages) Freescale Semiconductor, Inc – Ignores external trigger. Performs one conversion sequence and stops.

Port Integration Module (S12GPIMV0)
PAD3
PAD2-PAD0
Table 2-17. Port AD Pins AD7-0 (continued)
• 20 TSSOP: The ACMPO signal of the analog comparator is mapped to this pin when used with the
ACMP function. If the ACMP output is enabled (ACMPC[ACOPE]=1) the I/O state will be forced to
output.
• The ADC analog input channel signal AN3 and the related digital trigger input are mapped to this pin.
The ADC function has no effect on the output state. The input buffer is controlled by the related
ATDDIEN bit and the ADC trigger function.
• Pin interrupts can be generated if enabled in digital input or output mode.
• Signal priority:
20 TSSOP: ACMPO > GPO
Others: GPO
• The ADC analog input channel signals AN2-0 and their related digital trigger inputs are mapped to this
pin. The ADC function has no effect on the output state. The input buffers are controlled by the related
ATDDIEN bits and the ADC trigger functions.
• Pin interrupts can be generated if enabled in digital input or output mode.
• Signal priority:
GPO
2.4 PIM Ports - Memory Map and Register Definition
This section provides a detailed description of all PIM registers.
2.4.1 Memory Map
Table 2-18 shows the memory maps of all groups (for definitions see Table 2-2). Addresses 0x0000 to
0x0007 are only implemented in group G1 otherwise reserved.
Table 2-18. Block Memory Map (0x0000-0x027F)
Port
(A)
(B)
(C)
(D)
E
Global
Address
0x0000
0x0001
0x0002
0x0003
0x0004
0x0005
0x0006
0x0007
0x0008
0x0009
0x000A
:
0x000B
Register
PORTA—Port A Data Register¹
PORTB—Port B Data Register¹
DDRA—Port A Data Direction Register¹
DDRB—Port B Data Direction Register¹
PORTC—Port C Data Register¹
PORTD—Port D Data Register¹
DDRC—Port C Data Direction Register¹
DDRD—Port D Data Direction Register¹
PORTE—Port E Data Register
DDRE—Port E Data Direction Register
Non-PIM address range²
Access Reset Value
R/W
0x00
R/W
0x00
R/W
0x00
R/W
0x00
R/W
0x00
R/W
0x00
R/W
0x00
R/W
0x00
R/W
0x00
R/W
0x00
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Section/Page
2.4.3.1/2-164
2.4.3.2/2-165
2.4.3.3/2-166
2.4.3.4/2-166
2.4.3.5/2-167
2.4.3.6/2-168
2.4.3.7/2-168
2.4.3.8/2-169
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MC9S12G Family Reference Manual, Rev.1.01
Freescale Semiconductor
145
This document is valid for the S12G96 and the S12G128 device. All information related to other devices is preliminary.