MC9S12G Datasheet, PDF (249/1160 Pages) Freescale Semiconductor, Inc – Ignores external trigger. Performs one conversion sequence and stops.

Peripheral
Interrupt Requests
Interrupt Module (S12SINTV1)
Wake Up
CPU
Non I bit Maskable Channels
Vector
Address
I bit Maskable Channels
Interrupt
Requests
Figure 6-1. INT Block Diagram
IVBR
6.2 External Signal Description
The INT module has no external signals.
6.3 Memory Map and Register Definition
This section provides a detailed description of all registers accessible in the INT module.
6.3.1 Register Descriptions
This section describes in address order all the INT registers and their individual bits.
6.3.1.1 Interrupt Vector Base Register (IVBR)
Address: 0x0120
7
6
5
4
3
2
1
0
R
IVB_ADDR[7:0]
W
Reset
1
1
1
1
1
1
1
1
Figure 6-2. Interrupt Vector Base Register (IVBR)
Read: Anytime
Write: Anytime
MC9S12G Family Reference Manual, Rev.1.01
Freescale Semiconductor
249
This document is valid for the S12G96 and the S12G128 device. All information related to other devices is preliminary.