MC9S12G Datasheet, PDF (677/1160 Pages) Freescale Semiconductor, Inc – Ignores external trigger. Performs one conversion sequence and stops.

16 KByte Flash Module (S12FTMRG16K1V1)
21.3.2.10 EEPROM Protection Register (EEPROT)
The EEPROT register defines which EEPROM sectors are protected against program and erase operations.
Offset Module Base + 0x0009
7
6
R
0
DPOPEN
W
Reset
F¹
0
5
4
3
2
1
0
0
DPS[4:0]
0
F¹
F¹
F¹
F¹
F¹
= Unimplemented or Reserved
Figure 21-14. EEPROM Protection Register (EEPROT)
1 _{Loaded from IFR Flash configuration field, during reset sequence.}
The (unreserved) bits of the EEPROT register are writable with the restriction that protection can be added
but not removed. Writes must increase the DPS value and the DPOPEN bit can only be written from 1
(protection disabled) to 0 (protection enabled). If the DPOPEN bit is set, the state of the DPS bits is
irrelevant.
During the reset sequence, fields DPOPEN and DPS of the EEPROT register are loaded with the contents
of the EEPROM protection byte in the Flash configuration field at global address 0x3_FF0D located in
P-Flash memory (see Table 21-4) as indicated by reset condition F in Table 21-21. To change the
EEPROM protection that will be loaded during the reset sequence, the P-Flash sector containing the
EEPROM protection byte must be unprotected, then the EEPROM protection byte must be programmed.
If a double bit fault is detected while reading the P-Flash phrase containing the EEPROM protection byte
during the reset sequence, the DPOPEN bit will be cleared and DPS bits will be set to leave the EEPROM
memory fully protected.
Trying to alter data in any protected area in the EEPROM memory will result in a protection violation error
and the FPVIOL bit will be set in the FSTAT register. Block erase of the EEPROM memory is not possible
if any of the EEPROM sectors are protected.
Table 21-20. EEPROT Field Descriptions
Field
Description
7
DPOPEN
4–0
DPS[4:0]
EEPROM Protection Control
0 Enables EEPROM memory protection from program and erase with protected address range defined by DPS
bits
1 Disables EEPROM memory protection from program and erase
EEPROM Protection Size — The DPS[4:0] bits determine the size of the protected area in the EEPROM
memory as shown inTable 21-21 .
MC9S12G Family Reference Manual, Rev.1.01
Freescale Semiconductor
677
This document is valid for the S12G96 and the S12G128 device. All information related to other devices is preliminary.