MC9S12G Datasheet, PDF (281/1160 Pages) Freescale Semiconductor, Inc – Ignores external trigger. Performs one conversion sequence and stops.

S12S Debug Module (S12SDBG)
— CPU breakpoint entering BDM on breakpoint (BDM)
— CPU breakpoint executing SWI on breakpoint (SWI)
• Trigger mode independent of comparators
— TRIG Immediate software trigger
• Four trace modes
— Normal: change of flow (COF) PC information is stored (see Section 8.4.5.2.1, “Normal Mode)
for change of flow definition.
— Loop1: same as Normal but inhibits consecutive duplicate source address entries
— Detail: address and data for all cycles except free cycles and opcode fetches are stored
— Compressed Pure PC: all program counter addresses are stored
• 4-stage state sequencer for trace buffer control
— Tracing session trigger linked to Final State of state sequencer
— Begin and End alignment of tracing to trigger
8.1.4 Modes of Operation
The DBG module can be used in all MCU functional modes.
During BDM hardware accesses and whilst the BDM module is active, CPU monitoring is disabled. When
the CPU enters active BDM Mode through a BACKGROUND command, the DBG module, if already
armed, remains armed.
The DBG module tracing is disabled if the MCU is secure, however, breakpoints can still be generated
Table 8-1. Mode Dependent Restriction Summary
BDM
Enable
x
0
0
1
1
BDM
Active
x
0
1
0
1
MCU
Secure
1
0
0
0
0
Comparator
Matches Enabled
Yes
Yes
Yes
No
Breakpoints
Possible
Tagging
Possible
Yes
Yes
Only SWI
Yes
Active BDM not possible when not enabled
Yes
Yes
No
No
Tracing
Possible
No
Yes
Yes
No
MC9S12G Family Reference Manual, Rev.1.01
Freescale Semiconductor
281
This document is valid for the S12G96 and the S12G128 device. All information related to other devices is preliminary.