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MC9S12G Datasheet, PDF (826/1160 Pages) Freescale Semiconductor, Inc – Ignores external trigger. Performs one conversion sequence and stops. | |||
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64 KByte Flash Module (S12FTMRG64K1V1)
Table 24-15. FSTAT Field Descriptions
Field
Description
7
CCIF
Command Complete Interrupt Flag â The CCIF ï¬ag indicates that a Flash command has completed. The
CCIF ï¬ag is cleared by writing a 1 to CCIF to launch a command and CCIF will stay low until command
completion or command violation.
0 Flash command in progress
1 Flash command has completed
5
ACCERR
Flash Access Error Flag â The ACCERR bit indicates an illegal access has occurred to the Flash memory
caused by either a violation of the command write sequence (see Section 24.4.4.2) or issuing an illegal Flash
command. While ACCERR is set, the CCIF ï¬ag cannot be cleared to launch a command. The ACCERR bit is
cleared by writing a 1 to ACCERR. Writing a 0 to the ACCERR bit has no effect on ACCERR.
0 No access error detected
1 Access error detected
4
FPVIOL
3
MGBUSY
2
RSVD
Flash Protection Violation Flag âThe FPVIOL bit indicates an attempt was made to program or erase an
address in a protected area of P-Flash or EEPROM memory during a command write sequence. The FPVIOL
bit is cleared by writing a 1 to FPVIOL. Writing a 0 to the FPVIOL bit has no effect on FPVIOL. While FPVIOL
is set, it is not possible to launch a command or start a command write sequence.
0 No protection violation detected
1 Protection violation detected
Memory Controller Busy Flag â The MGBUSY ï¬ag reï¬ects the active state of the Memory Controller.
0 Memory Controller is idle
1 Memory Controller is busy executing a Flash command (CCIF = 0)
Reserved Bit â This bit is reserved and always reads 0.
1â0
Memory Controller Command Completion Status Flag â One or more MGSTAT ï¬ag bits are set if an error
MGSTAT[1:0] is detected during execution of a Flash command or during the Flash reset sequence. See Section 24.4.6,
âFlash Command Description,â and Section 24.6, âInitializationâ for details.
24.3.2.8 Flash Error Status Register (FERSTAT)
The FERSTAT register reï¬ects the error status of internal Flash operations.
Offset Module Base + 0x0007
7
R
0
W
Reset
0
6
5
4
3
2
0
0
0
0
0
0
0
0
0
0
= Unimplemented or Reserved
Figure 24-12. Flash Error Status Register (FERSTAT)
1
DFDIF
0
All ï¬ags in the FERSTAT register are readable and only writable to clear the ï¬ag.
0
SFDIF
0
MC9S12G Family Reference Manual, Rev.1.01
826
Freescale Semiconductor
This document is valid for the S12G96 and the S12G128 device. All information related to other devices is preliminary.
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