MC9S12G Datasheet, PDF (591/1160 Pages) Freescale Semiconductor, Inc – Ignores external trigger. Performs one conversion sequence and stops.

Serial Communication Interface (S12SCIV5)
To determine the value of a data bit and to detect noise, recovery logic takes samples at RT8, RT9, and
RT10. Table 18-18 summarizes the results of the data bit samples.
Table 18-18. Data Bit Recovery
RT8, RT9, and RT10 Samples
000
001
010
011
100
101
110
111
Data Bit Determination
0
0
0
1
0
1
1
1
Noise Flag
0
1
1
1
1
1
1
0
NOTE
The RT8, RT9, and RT10 samples do not affect start bit verification. If any
or all of the RT8, RT9, and RT10 start bit samples are logic 1s following a
successful start bit verification, the noise flag (NF) is set and the receiver
assumes that the bit is a start bit (logic 0).
To verify a stop bit and to detect noise, recovery logic takes samples at RT8, RT9, and RT10. Table 18-19
summarizes the results of the stop bit samples.
Table 18-19. Stop Bit Recovery
RT8, RT9, and RT10 Samples
000
001
010
011
100
101
110
111
Framing Error Flag
1
1
1
0
1
0
0
0
Noise Flag
0
1
1
1
1
1
1
0
In Figure 18-22 the verification samples RT3 and RT5 determine that the first low detected was noise and
not the beginning of a start bit. The RT clock is reset and the start bit search begins again. The noise flag
is not set because the noise occurred before the start bit was found.
MC9S12G Family Reference Manual, Rev.1.01
Freescale Semiconductor
591
This document is valid for the S12G96 and the S12G128 device. All information related to other devices is preliminary.