MC9S12G Datasheet, PDF (294/1160 Pages) Freescale Semiconductor, Inc – Ignores external trigger. Performs one conversion sequence and stops.

S12S Debug Module (S12SDBG)
Address: 0x0028
7
6
5
4
3
2
1
R
0
SZE
SZ
TAG
BRK
RW
RWE
W
Reset
0
0
0
0
0
0
0
= Unimplemented or Reserved
Figure 8-14. Debug Comparator Control Register DBGBCTL (Comparator B)
0
COMPE
0
Address: 0x0028
7
R
0
W
Reset
0
6
5
4
3
2
1
0
0
TAG
BRK
RW
RWE
0
0
0
0
0
0
= Unimplemented or Reserved
Figure 8-15. Debug Comparator Control Register DBGCCTL (Comparator C)
0
COMPE
0
Read: DBGACTL if COMRV[1:0] = 00
DBGBCTL if COMRV[1:0] = 01
DBGCCTL if COMRV[1:0] = 10
Write: DBGACTL if COMRV[1:0] = 00 and DBG not armed
DBGBCTL if COMRV[1:0] = 01 and DBG not armed
DBGCCTL if COMRV[1:0] = 10 and DBG not armed
Table 8-21. DBGXCTL Field Descriptions
Field
Description
7
SZE
(Comparators
A and B)
Size Comparator Enable Bit — The SZE bit controls whether access size comparison is enabled for the
associated comparator. This bit is ignored if the TAG bit in the same register is set.
0 Word/Byte access size is not used in comparison
1 Word/Byte access size is used in comparison
6
SZ
(Comparators
A and B)
Size Comparator Value Bit — The SZ bit selects either word or byte access size in comparison for the
associated comparator. This bit is ignored if the SZE bit is cleared or if the TAG bit in the same register is set.
0 Word access size is compared
1 Byte access size is compared
5
Tag Select— This bit controls whether the comparator match has immediate effect, causing an immediate
TAG
state sequencer transition or tag the opcode at the matched address. Tagged opcodes trigger only if they
reach the execution stage of the instruction queue.
0 Allow state sequencer transition immediately on match
1 On match, tag the opcode. If the opcode is about to be executed allow a state sequencer transition
4
BRK
Break— This bit controls whether a comparator match terminates a debug session immediately, independent
of state sequencer state. To generate an immediate breakpoint the module breakpoints must be enabled
using the DBGC1 bit DBGBRK.
0 The debug session termination is dependent upon the state sequencer and trigger conditions.
1 A match on this channel terminates the debug session immediately; breakpoints if active are generated,
tracing, if active, is terminated and the module disarmed.
MC9S12G Family Reference Manual, Rev.1.01
294
Freescale Semiconductor
This document is valid for the S12G96 and the S12G128 device. All information related to other devices is preliminary.