EP1SGX10C Datasheet, PDF (98/262 Pages) Altera Corporation – StratixGX FPGA Family

Stratix GX FPGA Family
Figure 65. M-RAM Row Unit Interface to Interconnect
C4 and C8 Interconnects R4 and R8 Interconnects
M-RAM Block
LAB
Direct Link
Interconnects
10
Up to 24
Row Interface Block
M-RAM Block to
LAB Row Interface
Block Interconnect Region
addressa
addressb
renwe_a
renwe_b
byteena_A[ ]
byteena_B[ ]
clocken_a
clocken_b
clock_a
clock_b
aclr_a
aclr_b
98
Preliminary
Altera Corporation