EP1SGX10C Datasheet, PDF (20/262 Pages) Altera Corporation – StratixGX FPGA Family

Stratix GX FPGA Family
Figure 12. Receiver Input Buffer
Input
Pins
Programmable
Termination
Programmable
Equalizer
Differential
Input
Buffer
Programmable Termination
The programmable termination can be statically set in the Quartus II
software. Figure 13 shows the setup for programmable receiver
termination.
Figure 13. Programmable Receiver Termination
50, 60, or 75 Ω
V_CM
Differential
Input
Buffer
50, 60, or 75 Ω
If external termination is used, then the receiver must be externally
terminated and biased to 1.1 V. Figure 14 shows an example of an external
termination/biasing circuit.
20
Preliminary
Altera Corporation