EP1SGX10C Datasheet, PDF (22/262 Pages) Altera Corporation – StratixGX FPGA Family

Stratix GX FPGA Family
Figure 15. Receiver PLL & CRU Circuit
Receiver PLL
÷ m (1)
Low-Speed TX_PLL_CLK
Inter Transceiver Routing (IQ1)
Global Clks, IO Bus, Gen Routing
RX CRUCLK
rx_locked
PFD
up
down
up
down
Charge Pump
VCO
and Loop Filter
Dedicated
Local
÷2
REFCLKB
Note to Figure 15:
(1) m = 8, 10 16, or 20.
rx_locktorefclk
rx_locktodata
RX_IN
rx_freqlocked[]
CRU
rx_riv[ ]
High-speed RCVD_CLK
Low-speed RCVD_CLK
The receiver PLLs and CRUs are capable of supporting up to 3.1875 Gbps.
The input clock frequency for –5 and –6 speed grade devices is limited to
650 MHz if designers use the REFCLKB pin or 325 MHz if designers use
the other clock routing resources. The maximum input clock frequency
for –7 speed grade devices is 312.5 MHz if designers use the REFCLKB pin
or 156.25 MHz with the other clock routing resources. An optional
RX_LOCKED port (active low signal) is available to indicate whether the
PLL is locked to the reference clock. The receiver PLL has a
programmable loop bandwidth, which can be set to low, medium, or
high. The loop bandwidth parameter can be statically set by the
Quartus II software.
22
Preliminary
Altera Corporation