EP1SGX10C Datasheet, PDF (232/262 Pages) Altera Corporation – StratixGX FPGA Family

Stratix GX FPGA Family
Table 121. EP1SGX25 Column Pin Global Clock External I/O Timing Parameters
Symbol
t_INSU
t_INH
t_OUTCO
t_INSUPLL
t_INHPLL
t_OUTCOPLL
-5 Speed Grade
Min
Max
-6 Speed Grade
Min
Max
-7 Speed Grade
Unit
Min
Max
1.790
1.883
2.120
ns
0.000
0.000
0.000
ns
2.000
5.194
2.000
5.569
2.000
6.381
ns
1.046
1.141
1.220
ns
0.000
0.000
0.000
ns
0.500
2.676
0.500
2.813
0.500
3.208
ns
Table 122. EP1SGX25 Row Pin Fast Regional Clock External I/O Timing Parameters
Symbol
t_INSU
t_INH
t_OUTCO
-5 Speed Grade
Min
Max
2.394
0.000
2.000
4.456
-6 Speed Grade
Min
Max
2.594
0.000
2.000
4.761
-7 Speed Grade
Unit
Min
Max
2.936
ns
0.000
ns
2.000
5.454
ns
Table 123. EP1SGX25 Row Pin Regional Clock External I/O Timing Parameters
Symbol
t_INSU
t_INH
t_OUTCO
t_INSUPLL
t_INHPLL
t_OUTCOPLL
-5 Speed Grade
Min
Max
-6 Speed Grade
Min
Max
-7 Speed Grade
Unit
Min
Max
1.970
2.109
2.377
ns
0.000
0.000
0.000
ns
2.000
4.880
2.000
5.246
2.000
6.013
ns
1.326
1.386
1.552
ns
0.000
0.000
0.000
ns
0.500
2.304
0.500
2.427
0.500
2.765
ns
Table 124. EP1SGX25 Row Pin Global Clock External I/O Timing Parameters (Part 1 of 2)
Symbol
t_INSU
t_INH
-5 Speed Grade
Min
Max
-6 Speed Grade
Min
Max
-7 Speed Grade
Unit
Min
Max
1.963
2.108
2.379
ns
0.000
0.000
0.000
ns
232
Preliminary
Altera Corporation