EP1SGX10C Datasheet, PDF (145/262 Pages) Altera Corporation – StratixGX FPGA Family

Figure 96. Clock Switchover Circuitry
SMCLKSW
Clock
Sense
PLLs & Clock Networks
Switch-Over
State Machine
CLK0_BAD
CLK1_BAD
Active Clock
CLKLOSS
CLKSWITCH
CLK0
CLK1
∆t
MUXOUT
n Counter
PFD
FBCLK
Note to Figure 96:
(1) PFD: phase frequency detector.
Enhanced PLL
There are two possible ways to use the clock switchover feature.
■ Designers can use automatic switchover circuitry for switching
between inputs of the same frequency. For example, in applications
that require a redundant clock with the same frequency as the
primary clock, the switchover state machine generates a signal that
controls the multiplexer select input on the bottom of Figure 96. In
this case, the secondary clock becomes the reference clock for the
PLL.
■ Designers can use the clkswitch input for user- or system-
controlled switch conditions. This is possible for same-frequency
switchover or to switch between inputs of different frequencies. For
example, if inclk0 is 66 MHz and inclk1 is 100 MHz, designers
must control the switchover because the automatic clock-sense
circuitry cannot monitor primary and secondary clock frequencies
with a frequency difference of more than ±20%. This feature is useful
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Preliminary