EP1SGX10C Datasheet, PDF (19/262 Pages) Altera Corporation – StratixGX FPGA Family

Transceiver Blocks
Programmable Transmitter Termination
The programmable termination can be statically set in the Quartus II
software. The values are 100 Ω, 120 Ω, 150 Ω, and off. Figure 11 shows the
setup for programmable termination.
Figure 11. Programmable Transmitter Termination
Programmable
Output
Driver
V_CM
50, 60, or 75 Ω
Receiver Path
This section describes the data path through the Stratix GX receiver (refer
to Figure 4 on page 11). Data travels through the Stratix GX receiver via
the following modules:
■ Input buffer
■ Clock Recovery Unit (CRU)
■ Deserializer
■ Pattern detector and word aligner
■ Rate matcher and channel aligner
■ 8B/10B decoder
■ Receiver logic array interface
Receiver Input Buffer
The Stratix GX receiver input buffer supports the 1.5-V PCML I/O
standard at a rate up to 3.1875 Gbps. Additional I/O standards, LVDS,
3.3-V PCML, and LVPECL can be supported when AC coupled. The
common mode of the input buffer is 1.1 V. The receiver can support
Stratix GX-to-Stratix GX DC coupling.
Figure 12 shows a diagram of the receiver input buffer, which contains:
■ Programmable termination
■ Programmable equalizer
Altera Corporation
19
Preliminary