EP1SGX10C Datasheet, PDF (234/262 Pages) Altera Corporation – StratixGX FPGA Family

Stratix GX FPGA Family
Table 127. EP1SGX40 Column Pin Global Clock External I/O Timing Parameters
Symbol
t_INSU
t_INH
t_OUTCO
t_INSUPLL
t_INHPLL
t_OUTCOPLL
-5 Speed Grade
Min
Max
-6 Speed Grade
Min
Max
-7 Speed Grade
Unit
Min
Max
2.033
2.184
2.451
ns
0.000
0.000
0.000
ns
2.000
5.689
2.000
6.116
2.000
7.010
ns
1.228
1.278
1.415
ns
0.000
0.000
0.000
ns
0.500
2.594
0.500
2.732
0.500
3.113
ns
Table 128. EP1SGX40 Row Pin Fast Regional Clock External I/O Timing Parameters
Symbol
t_INSU
t_INH
t_OUTCO
-5 Speed Grade
Min
Max
-6 Speed Grade
Min
Max
-7 Speed Grade
Unit
Min
Max
2.450
2.662
3.046
ns
0.000
0.000
0.000
ns
2.000
4.880
2.000
5.241
2.000
6.004
ns
Table 129. EP1SGX40 Row Pin Regional Clock External I/O Timing Parameters
Symbol
t_INSU
t_INH
t_OUTCO
t_INSUPLL
t_INHPLL
t_OUTCOPLL
-5 Speed Grade
Min
Max
-6 Speed Grade
Min
Max
-7 Speed Grade
Unit
Min
Max
2.398
2.567
2.938
ns
0.000
0.000
0.000
ns
2.000
4.932
2.000
5.336
2.000
6.112
ns
1.126
1.186
1.352
ns
0.000
0.000
0.000
ns
0.500
2.304
0.500
2.427
0.500
2.765
ns
Table 130. EP1SGX40 Row Pin Global Clock External I/O Timing Parameters (Part 1 of 2)
Symbol
t_INSU
t_INH
-5 Speed Grade
Min
Max
-6 Speed Grade
Min
Max
-7 Speed Grade
Unit
Min
Max
1.965
2.128
2.429
ns
0.000
0.000
0.000
ns
234
Preliminary
Altera Corporation