EP1SGX10C Datasheet, PDF (138/262 Pages) Altera Corporation – StratixGX FPGA Family

Stratix GX FPGA Family
clocking, programmable bandwidth, phase and delay control, and
dynamic PLL reconfiguration, the Stratix GX device’s enhanced PLLs
provide designers with complete control of their clocks and system
timing. The fast PLLs provide general purpose clocking with
multiplication and phase shifting as well as high-speed outputs for high-
speed differential I/O support. Enhanced and fast PLLs work together
with the Stratix GX high-speed I/O and advanced clock architecture to
provide significant improvements in system performance and
bandwidth.
The Quartus II software enables the PLLs and their features without
requiring any external devices. Table 38 shows which PLLs are available
for each Stratix GX device and their type. Table 39 shows the enhanced
PLL and fast PLL features in Stratix GX devices.
Table 38. Stratix GX Device PLL Availability
Device
1
EP1SGX10 v
EP1SGX25 v
EP1SGX40 v
Fast PLLs
2 3 (1) 4 (1) 7
v
v
v
v
Enhanced PLLs
8 9 (1) 10 (1) 5 (2) 6 (2) 11 (3) 12 (3)
vv
vv
v
v
v
v
v
Notes to Table 38:
(1) PLLs 3, 4, 9, and 10 are not available in Stratix GX devices. However, these PLLs are listed in Table 38 because the
Stratix GX PLL numbering scheme is consistent with Stratix devices.
(2) PLLs 5 and 6 each have eight single-ended outputs or four differential outputs.
(3) PLLs 11 and 12 each have one single-ended output.
Table 39. Stratix GX Enhanced PLL & Fast PLL Features (Part 1 of 2) Notes (1)–(8)
Feature
Clock multiplication and division
Phase shift
Delay shift
Clock switchover
PLL reconfiguration
Programmable bandwidth
Spread spectrum clocking
Programmable duty cycle
Number of internal clock outputs
Enhanced PLL
m/ (n × post-scale counter) (1)
Down to 156.25-ps increments (3),
(4)
250-ps increments for ±3 ns
v
v
v
v
v
6
Fast PLL
m/(post-scale counter) (2)
Down to 125-ps increments (3), (4)
v
3 (5)
138
Preliminary
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