EP1SGX10C Datasheet, PDF (53/262 Pages) Altera Corporation – StratixGX FPGA Family

Source-Synchronous Signaling with DPA
Table 20. Stratix GX Source-Synchronous Differential I/O Resources (Part 2 of 2)
Device
EP1SGX25D
EP1SGX25F
EP1SGX40D
EP1SGX40G
Fast PLLs
2
2
4 (4)
4 (4)
Pin Count
672
1,020
1,020
1,020
1,020
Receiver
Channels
(1)
Transmitter
Channels
(1)
39
39
39
39
39
39
45
45
45
45
Receiver &
Transmitter
Channel Speed
(Gbps) (2)
1
1
1
1
1
LEs
25,660
25,660
25,660
41,250
41,250
Notes to Table 20:
(1) This is the number of receiver or transmitter channels in the source-synchronous (I/O bank 1 and 2) interface of
the device.
(2) Receiver channels operate at 1,000 Mbps with DPA. Without DPA, the receiver channels operate at 840 Mbps.
(3) One of the two fast PLLs in EP1SGX10C and EP1SGX10D devices supports DPA.
(4) Two of the four fast PLLs in EP1SGX40D and EP1SGX40G devices support DPA
The receiver and transmitter channels are interleaved so that each I/O
row in I/O banks 1 and 2 of the device has one receiver channel and one
transmitter channel per row. Figures 39 and 40 show the fast PLL and
channels with DPA layout in EP1SGX10, EP1SGX25, and EP1SGX40
devices. In EP1SGX10 devices, only fast PLL 2 supports DPA operations.
Altera Corporation
53
Preliminary