EP1SGX10C Datasheet, PDF (162/262 Pages) Altera Corporation – StratixGX FPGA Family

Stratix GX FPGA Family
Figure 106. Control Signal Selection per IOE
Dedicated I/O
Clock [7..0]
I/O Interconnect
[15..0]
Local
Interconnect
io_coe
io_bclk[3..0]
io_bce[3..0]
io_bclr[3..0]
Local
Interconnect
io_cclr
Local
Interconnect
io_cce_out
Local
Interconnect
Local
Interconnect
io_cce_in
io_cclk
clk_out
ce_out
sclr/preset
clk_in
ce_in
aclr/preset
oe
io_boe[3..0]
In normal bidirectional operation, the input register can be used for input
data requiring fast setup times. The input register can have its own clock
input and clock enable separate from the OE and output registers. The
output register can be used for data requiring fast clock-to-output
performance. The OE register can be used for fast clock-to-output enable
timing. The OE and output register share the same clock source and the
same clock enable source from local interconnect in the associated LAB,
dedicated I/O clocks, and the column and row interconnects. Figure 107
shows the IOE in bidirectional configuration.
162
Preliminary
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