EP1SGX10C Datasheet, PDF (152/262 Pages) Altera Corporation – StratixGX FPGA Family

Stratix GX FPGA Family
In addition to the phase-shift feature, the fine tune clock delay shift
feature provides advanced time delay shift control on each of the four
PLL outputs. Each PLL output shifts in 250-ps increments for a range of
–3.0 ns to +3.0 ns between any two outputs using discrete delay elements.
Total delay shift between any two PLL outputs must be less than 3 ns. For
example, shifts on outputs of –1 and +2 ns is allowed, but not –1 and
+2.5 ns. There is some delay variation due to process, voltage, and
temperature. Only the clock delay shift blocks can be controlled during
system operation for dynamic clock delay control.
Spread-Spectrum Clocking
The Stratix GX device’s enhanced PLLs use spread-spectrum technology
to reduce electromagnetic interference generation from a system by
distributing the energy over a broader frequency range. The enhanced
PLL typically provides 0.5% down spread modulation using a triangular
profile. The modulation frequency is programmable. Enabling spread
spectrum for a PLL affects all of its outputs.
f
Lock Detect
The lock output indicates that there is a stable clock output signal in
phase with the reference clock. Without any additional circuitry, the lock
signal may toggle as the PLL begins tracking the reference clock.
Designers may need to gate the lock signal for use as a system control.
The lock signal from the locked port can drive the logic array or an output
pin.
Whenever the PLL loses lock for any reason (be it excessive inclk jitter,
clock switchover, PLL reconfiguration, power supply noise etc.), the PLL
must be reset with the areset signal for correct phase shift operation. If
the phase relationship between the input clock versus output clock, and
between different output clocks from the PLL is not important in the
design, then the PLL need not be reset.
See the Stratix GX FPGA Errata Sheet for more information on
implementing the gated lock signal in the design.
Programmable Duty Cycle
The programmable duty cycle allows enhanced PLLs to generate clock
outputs with a variable duty cycle. This feature is supported on each
enhanced PLL post-scale counter (g0..g3, l0..l3, e0..e3). The duty cycle
setting is achieved by a low and high time count setting for the post-scale
dividers. The Quartus II software uses the frequency input and the
required multiply or divide rate to determine the duty cycle choices.
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Preliminary
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