EP1SGX10C Datasheet, PDF (175/262 Pages) Altera Corporation – StratixGX FPGA Family

I/O Structure
■ LVDS
■ LVPECL
■ 3.3-V PCML
■ HyperTransport
■ Differential HSTL (on input/output clocks only)
■ Differential SSTL (on output column clock pins only)
■ GTL/GTL+
■ 1.5-V HSTL class I and II
■ 1.8-V HSTL Class I and II
■ SSTL-3 class I and II
■ SSTL-2 class I and II
■ SSTL-18 class I and II
■ CTT
Table 48 describes the I/O standards supported by Stratix GX devices.
Table 48. Stratix GX Supported I/O Standards (Part 1 of 2)
I/O Standard
Input Reference Output Supply
Type
Voltage (V_REF) Voltage (V_CCIO)
(V)
(V)
LVTTL
Single-ended
N/A
3.3
LVCMOS
Single-ended
N/A
3.3
2.5 V
Single-ended
N/A
2.5
1.8 V
Single-ended
N/A
1.8
1.5 V
Single-ended
N/A
1.5
3.3-V PCI
Single-ended
N/A
3.3
3.3-V PCI-X 1.0
Single-ended
N/A
3.3
LVDS
Differential
N/A
3.3
LVPECL
Differential
N/A
3.3
3.3-V PCML
Differential
N/A
3.3
HyperTransport
Differential
N/A
2.5
Differential HSTL (1)
Differential
0.75
1.5
Differential SSTL (2)
Differential
1.25
2.5
GTL
Voltage-referenced
0.8
N/A
GTL+
Voltage-referenced
1.0
N/A
1.5-V HSTL class I and II Voltage-referenced
0.75
1.5
1.8-V HSTL class I and II Voltage-referenced
0.9
1.8
SSTL-18 class I and II
Voltage-referenced
0.90
1.8
SSTL-2 class I and II
Voltage-referenced
1.25
2.5
Board
Termination
Voltage (V_TT)
(V)
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
0.75
1.25
1.20
1.5
0.75
0.9
0.90
1.25
Altera Corporation
175
Preliminary