EP1SGX10C Datasheet, PDF (151/262 Pages) Altera Corporation – StratixGX FPGA Family

PLLs & Clock Networks
Clock Feedback
The following four feedback modes in Stratix GX device enhanced PLLs
allow multiplication and/or phase and delay shifting:
■ Zero delay buffer: The external clock output pin is phase-aligned
with the clock input pin for zero delay.
■ External feedback: The external feedback input pin, FBIN, is
phase-aligned with the clock input, CLK, pin. Aligning these clocks
allows the designer to remove clock delay and skew between
devices. This mode is only possible for PLLs 5 and 6. PLLs 5 and 6
each support feedback for one of the dedicated external outputs,
either one single-ended or one differential pair. In this mode, one e
counter feeds back to the PLL FBIN input, becoming part of the
feedback loop.
■ Normal mode: If an internal clock is used in this mode, it is
phase-aligned to the input clock pin. The external clock output pin
will have a phase delay relative to the clock input pin if connected in
this mode. The designer defines which internal clock output from the
PLL should be phase-aligned to the internal clock pin.
■ No compensation: In this mode, the PLL will not compensate for any
clock networks or external clock outputs.
Phase & Delay Shifting
Stratix GX device enhanced PLLs provide advanced programmable
phase and clock delay shifting. For phase shifting, designers can specify
a phase shift (in degrees or time units) for each PLL clock output port or
for all outputs together in one shift. Phase-shifting values in time units are
allowed with a resolution range of 160 to 420 ps. This resolution is a
function of frequency input and the multiplication and division factors.
In other words, it is a function of the VCO period equal to one-eighth of
the VCO period. Each clock output counter can choose a different phase
of the VCO period from up to eight taps. Designers can use this clock
output counter along with an initial setting on the post-scale counter to
achieve a phase-shift range for the entire period of the output clock. The
phase tap feedback to the m counter can shift all outputs to a single phase
or delay. The Quartus II software automatically sets the phase taps and
counter settings according to the phase shift entered.
Altera Corporation
151
Preliminary