EP1SGX10C Datasheet, PDF (32/262 Pages) Altera Corporation – StratixGX FPGA Family

Stratix GX FPGA Family
Loopback Modes
The Stratix GX transceiver has built-in loopback modes to aid in debug
and testing. The loopback modes are set in the Stratix GX MegaWizard
Plug-In Manager in the Quartus II software. Only one loopback mode can
be set at any single instance of the transceiver block. The loopback mode
applies to all used channels in a transceiver block.
The available loopback modes are:
■ Serial loopback
■ Parallel loopback
■ Reverse serial loopback
Serial Loopback
Serial loopback exercises all the transceiver logic except for the output
buffer and input buffer. The loopback function is dynamically switchable
through the rx_slpbk port on a channel by channel basis. The V_OD of the
output is limited to 400 mV when the serial loopback option is selected.
Figure 23 shows the data path in serial loopback mode.
Figure 23. Data Path in Serial Loopback Mode
Deserializer
Word
Aligner
Clock
Recovery
Unit
BIST PRBS
Verifier
Channel
Aligner
Rate
Matcher
8B/10B
Decoder
Byte
Deserializer
BIST
Incremental
Verifier
Phase
Compensation
FIFO
Serializer
Active Path
Non-active Path
8B/10B
Encoder
BIST PRBS
Generator
Byte
Serializer
Phase
Compensation
FIFO
BIST
Generator
32
Preliminary
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