EP1SGX10C Datasheet, PDF (3/262 Pages) Altera Corporation – StratixGX FPGA Family

Features
Table 1. Stratix GX Device Features
Feature
LEs
Transceiver channels
Source-synchronous channels
M512 RAM blocks (32 × 18 bits)
M4K RAM blocks (128 × 36 bits)
M-RAM blocks (4K ×144 bits)
Total RAM bits
Digital signal processing (DSP) blocks
Embedded multipliers (1)
PLLs
EP1SGX10C
EP1SGX10D
10,570
4, 8
22
94
60
1
920,448
6
48
4
EP1SGX25C
EP1SGX25D
EP1SGX25F
25,660
4, 8, 16
39
224
138
2
1,944,576
10
80
4
EP1SGX40D
EP1SGX40G
41,250
8, 20
45
384
183
4
3,423,744
14
112
8
Note to Table 1:
(1) This parameter lists the total number of 9- × 9-bit multipliers for each device. For the total number of 18- × 18-bit
multipliers per device, divide the total number of 9- × 9-bit multipliers by 2. For the total number of 36- × 36-bit
multipliers per device, decide the total number of 9- × 9-bit multipliers by 8.
Stratix GX devices are available in space-saving FineLine BGA^® packages
(refer to Tables 2 and 3), and in multiple speed grades (refer to Table 4).
Stratix GX devices support vertical migration within the same package
(that is, the designer can migrate between the EP1SGX10C and
EP1SGX25C devices in the 672-pin FineLine BGA package). See the
Stratix GX device pin tables for more information. Vertical migration
means that designers can migrate to devices whose dedicated pins,
configuration pins, and power pins are the same for a given package
across device densities. For I/O pin migration across densities, the
designer must cross-reference the available I/O pins using the device pin-
outs for all planned densities of a given package type, to identify which
I/O pins it is possible to migrate. The Quartus II software can
automatically cross reference and place all pins for migration when given
a device migration list.
Table 2. Stratix GX Package Options & I/O Pin Counts (Part 1
of 2) Note (1)
Device
EP1SGX10C
EP1SGX10D
EP1SGX25C
672-Pin FineLine BGA
362
362
455
1,020-Pin FineLine BGA
Altera Corporation
3
Preliminary