EP1SGX10C Datasheet, PDF (237/262 Pages) Altera Corporation – StratixGX FPGA Family

Timing Model
Table 132. Stratix GX I/O Standard Row Pin Input Delay Adders (Part 2 of 2)
I/O Standard
1.5-V HSTL class II
1.8-V HSTL class I
1.8-V HSTL class II
LVDS (1)
LVPECL (1)
3.3-V PCML (1)
HyperTransport (1)
-5 Speed Grade
Min
Max
0
70
70
40
–50
330
80
-6 Speed Grade
Min
Max
0
73
73
42
–53
346
84
-7 Speed Grade
Unit
Min
Max
0
ps
83
ps
83
ps
48
ps
–61
ps
397
ps
96
ps
Table 133. Stratix GX I/O Standard Output Delay Adders for Fast Slew Rate on Column Pins (Part 1 of 2)
Standard
LVCMOS
3.3-V LVTTL
2.5-V LVTTL
1.8-V LVTTL
1.5-V LVTTL
GTL
2 mA
4 mA
8 mA
12 mA
24 mA
4 mA
8 mA
12 mA
16 mA
24 mA
2 mA
8 mA
12 mA
16 mA
2 mA
8 mA
12 mA
2 mA
4 mA
8 mA
-5 Speed Grade
Min
Max
570
570
350
130
0
570
350
130
70
0
830
250
140
100
420
350
350
1,740
1,160
690
–150
-6 Speed Grade
Min
Max
599
599
368
137
0
599
368
137
74
0
872
263
147
105
441
368
368
1,827
1,218
725
–157
-7 Speed Grade
Unit
Min
Max
689
ps
689
ps
423
ps
157
ps
0
ps
689
ps
423
ps
157
ps
85
ps
0
ps
1,002
ps
302
ps
169
ps
120
ps
507
ps
423
ps
423
ps
2,101
ps
1,400
ps
833
ps
–181
ps
Altera Corporation
237
Preliminary