EP1SGX10C Datasheet, PDF (25/262 Pages) Altera Corporation – StratixGX FPGA Family

Transceiver Blocks
Figure 17 shows the word aligner in bit-slip mode.
Figure 17. Word Aligner in Bit-Slip Mode
Word Aligner
Patterm Detector
Manual
Alignment
Mode
10-Bit
Mode
16-Bit
Mode
7-Bit
Mode
Bit-Slip
Mode
A1A2
Mode
A1A1A2A2
Mode
In the bit-slip mode, the byte boundary can be modified by a barrel shifter
to slip the byte boundary one bit at a time via a user-controlled bit-slip
port. The bit-slip mode supports both 8-bit and 10-bit datapaths
operating in a single or double-width mode.
The pattern detector is active in the bit-slip mode, and it will detect the
user-defined pattern that is specified in the MegaWizard^® Plug-In
Manager.
The bit-slip mode is available only in basic mode and SONET mode.
Figure 18 shows the word aligner in 16-bit mode.
Altera Corporation
25
Preliminary