EP1SGX10C Datasheet, PDF (199/262 Pages) Altera Corporation – StratixGX FPGA Family

Operating Conditions
Table 66. Stratix GX Transceiver Block AC Specification (Part 1 of 3)
Symbol /
Description
Conditions
-5 Commercial
Speed Grade (5)
-6 Commercial &
Industrial Speed
Grade
(5)
-7 Commercial &
Industrial Speed
Grade
(5)
Min
Power per
quadrant
(PCS + PMA)
3.125 Gbps,
400-mV V_{o d}
0 pre-
emphasis
Dedicated Reference Clock
REFCLK
Jitter
tolerance
(peak-to-
peak)
Jitter
components
<20 MHz
Wideband
REFCLK
25
(reference
input clock
frequency)–
dedicated
refclkb
pins
REFCLK
25
(reference
input clock
frequency)–
PLD clock
resources
Receiver
Serial data Commercial / 614
rate (general) industrial
Serial data Commercial / 500
rate (8B/10B industrial
encoded)
Parallel
20
transceiver/
logic array
interface
speed
Rate
matching
frequency
tolerance
XAUI mode
only
Receiver total @
jitter
3.125 Gbps
tolerance
Typ Max Min
450
20
50
650 25
325 25
3,187.5 614
3,187.5 500
398.4 20
±100
0.65
Typ Max Min
450
20
50
650 25
325 25
3,187.5 614
3,187.5 500
375 20
±100
0.65
Typ Max
20
50
312.5
156.25
2,500
2,500
312.5
±100
Unit
mW
ps
ps
MHz
MHz
Mbps
Mbps
MHz
ppm
UI
Altera Corporation
199
Preliminary