EP1SGX10C Datasheet, PDF (257/262 Pages) Altera Corporation – StratixGX FPGA Family

High-Speed I/O Specification
Table 149. Enhanced PLL Specifications for -7 Speed Grade (Part 2 of 2)
Symbol
Parameter
Min Typ
Max
Unit
t_LSKEW
Clock skew between two external clock
±50
ps
outputs driven by the same counter
t_SKEW
Clock skew between two external clock
±75
ps
outputs driven by the different counters
with the same settings
f_SS
Spread spectrum modulation frequency 30
150
kHz
% spread Percentage spread for spread
0.5
spectrum frequency (9)
0.6
%
t_ARESET
Minimum pulse width on areset
10
ns
signal
Notes to Tables 147 through 149:
(1) The minimum input clock frequency to the PFD (f_IN/N) must be at least 3 MHz for Stratix device enhanced PLLs.
(2) See “Maximum Input & Output Clock Rates” on page 245.
(3) t_FCOMP can also equal 50% of the input clock period multiplied by the pre-scale divider n (whichever is less).
(4) This parameter is timing analyzed by the Quartus II software because the scanclk and scandata ports can be
driven by the logic array.
(5) Actual jitter performance may vary based on the system configuration.
(6) Total required time to reconfigure and lock is equal to t_DLOCK + t_CONFIG. If only post-scale counters and delays are
changed, then t_DLOCK is equal to 0.
(7) The VCO range is limited to 500 to 800 MHz when the spread spectrum feature is selected.
(8) Lock time is a function of PLL configuration and may be significantly faster depending on bandwidth settings or
feedback counter change increment.
(9) Exact, user-controllable value depends on the PLL settings.
(10) The LOCK circuit on Stratix PLLs does not work for industrial devices below -20C unless the PFD frequency > 200
MHz. See the Stratix FPGA Errata Sheet for more information on the PLL.
Altera Corporation
257
Preliminary