EP1SGX10C Datasheet, PDF (23/262 Pages) Altera Corporation – StratixGX FPGA Family

Transceiver Blocks
Table 10 lists the adjustable parameters of the receiver PLL and CRU. All
the parameters listed are statically programmable in the Quartus II
software.
Table 10. Receiver PLL & CRU Adjustable Parameters
Parameter
Input reference frequency range
Data rate support
Multiplication factor (W)
PPM detector
Bandwidth
Run length detector
Specifications
25 MHz to 650 MHz
500 Mbps to 3.1875 Gbps
2, 4, 5, 8, 10, 16, or 20 (1)
125, 250, 500, 1,000
Low, medium, high
10-bit or 20-bit mode: 5 to 160 in steps of
5
8-bit or 16-bit mode: 4 to 128 in steps of 4
Note to Table 10:
(1) Multiplication factors 2, 4, and 5 can only be achieved with the use of the pre-
divider on the REFCLKB port or if the CRU is trained with the low speed clock
from the transmitter PLL.
The CRU has a built-in switchover circuit to select whether the
voltage-controlled oscillator of the PLL is trained by the reference clock or
the data. The optional port rx_freqlocked can be used to monitor
when the CRU is in locked to data mode.
In the automatic mode, the following conditions must be met for the CRU
to switch from locked to reference to locked to data mode:
■ The CRU PLL is within the prescribed PPM frequency threshold
setting (125 PPM, 250 PPM, 500 PPM, 1,000 PPM) of the CRU
reference clock.
■ The reference clock and CRU PLL output are phase matched (phases
are within .08 UI).
The automatic switchover circuit can be overridden by using the optional
ports rx_lockedtorefclk and rx_locktodata. Table 11 shows the
possible combinations of these two signals.
If the rx_lockedtorefclk and rx_locktodata ports are not used,
the default is auto mode.
Altera Corporation
23
Preliminary