EP1SGX10C Datasheet, PDF (84/262 Pages) Altera Corporation – StratixGX FPGA Family

Stratix GX FPGA Family
single block of RAM ideal for data packet storage. The different-sized
blocks allow Stratix GX devices to efficiently support variable-sized
memory in designs.
The Quartus II software automatically partitions the user-defined
memory into the embedded memory blocks using the most efficient size
combinations. The designer can also manually assign the memory to a
specific block size or a mixture of block sizes.
M512 RAM Block
The M512 RAM block is a simple dual-port memory block and is useful
for implementing small FIFO buffers, DSP, and clock domain transfer
applications. Each block contains 576 RAM bits (including parity bits).
M512 RAM blocks can be configured in the following modes:
■ Simple dual-port RAM
■ Single-port RAM
■ FIFO
■ ROM
■ Shift register
When configured as RAM or ROM, the designer can use an initialization
file to pre-load the memory contents.
The memory address depths and output widths can be configured as
512 × 1, 256 × 2, 128 × 4, 64 × 8 (64 × 9 bits with parity), and 32 × 16
(32 × 18 bits with parity). Mixed-width configurations are also possible,
allowing different read and write widths. Table 24 summarizes the
possible M512 RAM block configurations.
Table 24. M512 RAM Block Configurations (Simple Dual-Port RAM)
Write Port
Read Port
512 × 1 256 × 2 128 × 4 64 × 8 32 × 16 64 × 9 32 × 18
512 × 1 v
v
v
v
v
256 × 2 _v
v
v
v
v
128 × 4 _v
v
v
v
64 × 8
v
v
v
32 × 16 _v
v
v
v
64 × 9
v
32 × 18
v
84
Preliminary
Altera Corporation