EP1SGX10C Datasheet, PDF (90/262 Pages) Altera Corporation – StratixGX FPGA Family

Stratix GX FPGA Family
Figure 60. M4K RAM Block Control Signals
Dedicated
8
Row LAB
Clocks
Local
Interconnect
Local
Interconnect
Local
Interconnect
Local
Interconnect
Local
Interconnect
clocken_a
alcr_a
renwe_b
clock_b
clock_a
renwe_a
alcr_b
clocken_b
Local
Interconnect
Local
Interconnect
Local
Interconnect
Local
Interconnect
Local
Interconnect
Figure 61. M4K RAM Block LAB Row Interface
C4 and C8
Interconnects
Direct link
10
interconnect
to adjacent LAB
Direct link
interconnect
from adjacent LAB
dataout
M4K RAM
Block
Byte enable
Clocks
Control
Signals
R4 and R8
Interconnects
Direct link
interconnect
to adjacent LAB
Direct link
interconnect
from adjacent LAB
address datain
8
M4K RAM Block Local
Interconnect Region
LAB Row Clocks
90
Preliminary
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