EP1SGX10C Datasheet, PDF (135/262 Pages) Altera Corporation – StratixGX FPGA Family

PLLs & Clock Networks
Figure 89. Regional Clock Bus
Global Clock Network [15..0]
Regional Clock Network [3..0]
Fast Regional Clock Network [1..0]
Clocks Available
to a Quadrant
or Half-Quadrant
Clock [21:0]
Vertical I/O Cell
IO_CLK[7..0]
Lab Row Clock [7..0]
Horizontal I/O
Cell IO_CLK[7..0]
IOE clocks have horizontal and vertical block regions that are clocked by
eight I/O clock signals chosen from the 22-quadrant or half-quadrant
clock resources. Figures 90 and 91 show the quadrant and half-quadrant
relationship to the I/O clock regions, respectively. The vertical regions
(column pins) have less clock delay than the horizontal regions (row
pins).
Altera Corporation
135
Preliminary