EP1SGX10C Datasheet, PDF (142/262 Pages) Altera Corporation – StratixGX FPGA Family

Stratix GX FPGA Family
Figure 94. Global & Regional Clock Connections From Top Clock Pins & Enhanced PLL Outputs Note (1)
PLL5_OUT[3..0] CLK14
PLL5_FB CLK15
CLK12
CLK13
Regional RCLK14
Clocks RCLK15
Global
Clocks
Regional
Clocks
RCLK4
RCLK5
E[0..3]
PLL 5
PLL 11
L0 L1 G0 G1 G2 G3 G0 G1 G2 G3 L0 L1
L0 L1 G0 G1 G2 G3 G0 G1 G2 G3 L0 L1
PLL 6
PLL 12
PLL11_OUT
RCLK12
RCLK13
G12
G13
G14
G15
G4
G5
G6
G7
RCLK6
RCLK7
PLL12_OUT
PLL6_OUT[3..0] PLL6_FB
CLK6
CLK4
CLK5
Note to Figure 94:
(1) PLLs 5, 6, 11, and 12 are enhanced PLLs.
CLK7
142
Preliminary
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