EP1SGX10C Datasheet, PDF (214/262 Pages) Altera Corporation – StratixGX FPGA Family

Stratix GX FPGA Family
Preliminary & Final Timing
Timing models can have either preliminary or final status. The Quartus II
software displays an informational message during the design
compilation if the timing models are preliminary. Table 93 shows the
status of the Stratix GX device timing models.
Preliminary status means the timing model is subject to change. Initially,
timing numbers are created using simulation results, process data, and
other known parameters. These tests are used to make the preliminary
numbers as close to the actual timing parameters as possible.
Final timing numbers are based on actual device operation and testing.
These numbers reflect the actual performance of the device under worst-
case voltage and junction temperature conditions.
Table 93. Stratix GX Device Timing Model Status
Device
EP1SGX10
EP1SGX25
EP1SGX40
Preliminary
—
—
—
Final
v
v
v
Performance
Table 94 shows Stratix GX performance for some common designs. All
performance values were obtained with Quartus II software compilation
of LPM, or MegaCore functions for the FIR and FFT designs.
Table 94. Stratix Performance (Part 1 of 3) Notes (1), (2)
Resources Used
Performance
Applications
LE
16-to-1 multiplexer (1)
32-to-1 multiplexer (3)
16-bit counter
64-bit counter
TriMatrix Simple dual-port RAM 32 × 18
memory bit
M512 block _{FIFO 32 × 18 bit}
LEs
TriMatrix
Memory
Blocks
DSP
Blocks
-5
Speed
Grade
-6
Speed
Grade
-7
Speed
Grade
22
0
0 407.83 324.56 288.68
46
0
0 318.26 255.29 242.89
16
0
0 422.11 422.11 390.01
64
0
0 321.85 290.52 261.23
0
1
0 317.76 277.62 241.48
Units
MHz
MHz
MHz
MHz
MHz
30
1
0 319.18 278.86 242.54 MHz
214
Preliminary
Altera Corporation