EP1SGX10C Datasheet, PDF (230/262 Pages) Altera Corporation – StratixGX FPGA Family

Stratix GX FPGA Family
Table 115. EP1SGX10 Column Pin Global Clock External I/O Timing Parameters
Symbol
t_INSU
t_INH
t_OUTCO
t_INSUPLL
t_INHPLL
t_OUTCOPLL
-5 Speed Grade
Min
Max
-6 Speed Grade
Min
Max
-7 Speed Grade
Unit
Min
Max
1.785
1.814
2.087
ns
0.000
0.000
0.000
ns
2.000
5.057
2.000
5.438
2.000
6.214
ns
0.988
0.936
1.066
ns
0.000
0.000
0.000
ns
0.500
2.634
0.500
2.774
0.500
3.162
ns
Table 116. EP1SGX10 Row Pin Fast Regional Clock External I/O Timing Parameters
Symbol
t_INSU
t_INH
t_OUTCO
-5 Speed Grade
Min
Max
-6 Speed Grade
Min
Max
-7 Speed Grade
Unit
Min
Max
2.194
2.384
2.727
ns
0.000
0.000
0.000
ns
2.000
4.956
2.000
4.971
2.000
5.463
ns
Table 117. EP1SGX10 Row Pin Regional Clock External I/O Timing Parameters
Symbol
t_INSU
t_INH
t_OUTCO
t_INSUPLL
t_INHPLL
t_OUTCOPLL
-5 Speed Grade
Min
Max
-6 Speed Grade
Min
Max
-7 Speed Grade
Unit
Min
Max
2.244
2.413
2.574
ns
0.000
0.000
0.000
ns
2.000
4.906
2.000
4.942
2.000
5.616
ns
1.126
1.186
1.352
ns
0.000
0.000
0.000
ns
0.500
2.804
0.500
2.627
0.500
2.765
ns
Table 118. EP1SGX10 Row Pin Global Clock External I/O Timing Parameters (Part 1 of 2)
Symbol
t_INSU
t_INH
-5 Speed Grade
Min
Max
-6 Speed Grade
Min
Max
-7 Speed Grade
Unit
Min
Max
1.919
2.062
2.368
ns
0.000
0.000
0.000
ns
230
Preliminary
Altera Corporation