EP1SGX10C Datasheet, PDF (111/262 Pages) Altera Corporation – StratixGX FPGA Family

Digital Signal Processing Block
Figure 73. DSP Block Diagram for 18 × 18-Bit Configuration
Optional Serial Shift Register
Inputs from Previous
DSP Block
Multiplier Stage
DQ
ENA
CLRN
D
Optional Stage Configurable
as Accumulator or Dynamic
Adder/Subtractor
Q
Output Selection
Multiplexer
DQ
ENA
CLRN
ENA
CLRN
DQ
Adder/
Subtractor/
Accumulator
1
ENA
CLRN
DQ
DQ
ENA
CLRN
ENA
CLRN
Summation
Optional Serial
Shift Register
Outputs to
Next DSP Block
in the Column
DQ
ENA
CLRN
DQ
ENA
CLRN
DQ
ENA
CLRN
DQ
ENA
CLRN
DQ
ENA
CLRN
Summation Stage
for Adding Four
Multipliers Together
Adder/
Subtractor/
Accumulator
2
Optional Output
Register Stage
DQ
ENA
CLRN
Optional Pipeline
Register Stage
Optional Input Register
Stage with Parallel Input or
Shift Register Configuration
to MultiTrack
Interconnect
Altera Corporation
111
Preliminary