EP1SGX10C Datasheet, PDF (176/262 Pages) Altera Corporation – StratixGX FPGA Family

Stratix GX FPGA Family
Table 48. Stratix GX Supported I/O Standards (Part 2 of 2)
I/O Standard
Input Reference Output Supply
Type
Voltage (V_REF) Voltage (V_CCIO)
(V)
(V)
SSTL-3 class I and II
Voltage-referenced
1.5
3.3
AGP (1× and 2×)
Voltage-referenced
1.32
3.3
CTT
Voltage-referenced
1.5
3.3
Notes to Table 48:
(1) This I/O standard is only available on input and output clock pins.
(2) This I/O standard is only available on output column clock pins.
Board
Termination
Voltage (V_TT)
(V)
1.5
N/A
1.5
f
For more information on I/O standards supported by Stratix GX
devices, see the Selectable I/O Standards in Stratix & Stratix GX Devices
chapter of the Stratix Device Handbook, Volume 2.
Stratix GX devices contain eight I/O banks in addition to the four
enhanced PLL external clock out banks, as shown in Figure 113. The four
I/O banks on the right and left of the device contain circuitry to support
high-speed differential I/O for LVDS, LVPECL, 3.3-V PCML, and
HyperTransport inputs and outputs. These banks support all I/O
standards listed in Table 48 except PCI I/O pins or PCI-X 1.0, GTL, SSTL-
18 Class II, and HSTL Class II outputs. The top and bottom I/O banks
support all single-ended I/O standards. Additionally, Stratix GX devices
support four enhanced PLL external clock output banks, allowing clock
output capabilities such as differential support for SSTL and HSTL.
Table 49 shows I/O standard support for each I/O bank.
176
Preliminary
Altera Corporation