EP1SGX10C Datasheet, PDF (95/262 Pages) Altera Corporation – StratixGX FPGA Family

TriMatrix Memory
Figure 63. EP1SGX40 Device with M-RAM Interface Locations Note (1)
M-RAM interface to
top, bottom, and side opposite
of block-to-block border.
Independent M-RAM blocks
interface to top, bottom, and side facing
device perimeter for easy access
to horizontal I/O pins.
M-RAM
Block
M-RAM
Block
M-RAM
Block
M-RAM
Block
DSP
Blocks
M512
Blocks
LABs
DSP
Blocks
Note to Figure 63:
(1) Device shown is an EP1SGX40 device. The number and position of M-RAM blocks varies in other devices.
The M-RAM block local interconnect is driven by the R4, R8, C4, C8, and
direct link interconnects from adjacent LABs. For independent M-RAM
blocks, up to 10 direct link address and control signal input connections
to the M-RAM block are possible from the left adjacent LABs for M-RAM
Altera Corporation
95
Preliminary