EP1SGX10C Datasheet, PDF (127/262 Pages) Altera Corporation – StratixGX FPGA Family

Digital Signal Processing Block
The DSP block is divided into eight block units that interface with eight
LAB rows on the left and right. Each block unit can be considered half of
an 18 × 18-bit multiplier sub-block with 18 inputs and 18 outputs. A local
interconnect region is associated with each DSP block. Like an LAB, this
interconnect region can be fed with 10 direct link interconnects from the
LAB to the left or right of the DSP block in the same row. All row and
column routing resources can access the DSP block’s local interconnect
region. The outputs also work similarly to LAB outputs as well. Nine
outputs from the DSP block can drive to the left LAB through direct link
interconnects and nine can drive to the right LAB though direct link
interconnects. All 18 outputs can drive to all types of row and column
routing. Outputs can drive right- or left-column routing. Figures 83 and
84 show the DSP block interfaces to LAB rows.
Figure 83. DSP Block Interconnect Interface
DSP Block
MultiTrack
Interconnect
OA[17..0]
A1[17..0]
OB[17..0]
MultiTrack
Interconnect
B1[17..0]
OC[17..0]
A2[17..0]
OD[17..0]
B2[17..0]
OE[17..0]
A3[17..0]
OF[17..0]
B3[17..0]
OG[17..0]
A4[17..0]
OH[17..0]
B4[17..0]
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127
Preliminary