EP1SGX10C Datasheet, PDF (208/262 Pages) Altera Corporation – StratixGX FPGA Family

Stratix GX FPGA Family
Table 77. PCI-X Specifications (Part 2 of 2)
Symbol
V_{O H}
Parameter
High-level output voltage
Conditions
I_{O U T} = –500 µA
V_{O L}
Low-level output voltage I_{O U T} = 1,500 µA
Minimum
0.9 ×
V_{C C I O}
Typical
Maximum
0.1 ×
V_{C C I O}
Units
V
V
Table 78. GTL+ I/O Specifications
Symbol
V_TT
V_REF
V_IH
V_IL
Parameter
Termination voltage
Reference voltage
High-level input voltage
Low-level input voltage
Conditions
V_OL
Low-level output voltage I_OL = 36 mA (1)
Minimum
1.35
0.88
V_REF + 0.1
Typical
1.5
1.0
Maximum
1.65
1.12
V_{R E F} –
0.1
0.65
Units
V
V
V
V
V
Table 79. GTL I/O Specifications
Symbol
V_TT
V_REF
V_IH
Parameter
Termination voltage
Reference voltage
High-level input voltage
Conditions
V_IL
Low-level input voltage
V_OL
Low-level output voltage I_OL = 40 mA (1)
Minimum
1.14
0.74
V_REF +
0.05
Typical
1.2
0.8
Maximum
1.26
0.86
V_{R E F} –
0.05
0.4
Units
V
V
V
V
V
Table 80. SSTL-18 Class I Specifications (Part 1 of 2)
Symbol
V_CCIO
V_REF
V_TT
V_IH(DC)
Parameter
Output supply voltage
Reference voltage
Termination voltage
High-level DC input voltage
Conditions
V_IL(DC)
Low-level DC input voltage
Minimum
1.65
0.8
V_{R E F} – 0.04
V_{R E F} +
0.125
Typical
1.8
0.9
V_{R E F}
Maximum
1.95
1.0
V_{R E F} + 0.04
V_{R E F} –
0.125
Units
V
V
V
V
V
208
Preliminary
Altera Corporation