EP1SGX10C Datasheet, PDF (91/262 Pages) Altera Corporation – StratixGX FPGA Family

TriMatrix Memory
M-RAM Block
The largest TriMatrix memory block, the M-RAM block, is useful for
applications where a large volume of data must be stored on-chip. Each
block contains 589,824 RAM bits (including parity bits). The M-RAM
block can be configured in the following modes:
■ True dual-port RAM
■ Simple dual-port RAM
■ Single-port RAM
■ FIFO RAM
The designer cannot use an initialization file to initialize the contents of a
M-RAM block. All M-RAM block contents power up to an undefined
value. Only synchronous operation is supported in the M-RAM block, so
all inputs are registered. Output registers can be bypassed. The memory
address and output width can be configured as 64K × 8 (or 64K × 9 bits),
32K × 16 (or 32K × 18 bits), 16K × 32 (or 16K × 36 bits), 8K × 64 (or
8K × 72 bits), and 4K × 128 (or 4K × 144 bits). The 4K × 128 configuration
is unavailable in true dual-port mode because there are a total of 144 data
output drivers in the block. Mixed-width configurations are also possible,
allowing different read and write widths. Tables 28 and 29 summarizes
the possible M-RAM block configurations:
Table 28. M-RAM Block Configurations (Simple Dual-Port)
Read Port
64K × 9
32K × 18
16K × 36
8K × 72
4K × 144
64K × 9
v
v
v
v
Write Port
32K × 18 16K × 36
v
v
v
v
v
v
v
v
8K × 72
v
v
v
v
4K × 144
v
Altera Corporation
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Preliminary