EP1SGX10C Datasheet, PDF (60/262 Pages) Altera Corporation – StratixGX FPGA Family

Stratix GX FPGA Family
The DPA data-realignment circuitry allows further realignment beyond
what the J multiplication factor allows. Designers can set the J
multiplication factor to be 8 or 10. However, because data must be
continuously clocked in on each low-speed clock cycle, the upcoming bit
to be realigned and previous n − 1 bits of data are selected each time the
data realignment logic’s counter passes n − 1. At this point the data is
selected entirely from bit-slip register 3 (see Figure 44) as the counter is
reset to 0. The logic array receives a new valid byte of data on the next
divided low speed clock cycle. Figure 44 shows the data realignment
logic output selection from data in the data realignment register 2 and
data realignment register 3 based on its current counter value upon
continuous request of data slipping from the logic array.
Figure 44. DPA Data Realigner
Bit Slip Bit Slip
Register 2 Register 3
Bit Slip Bit Slip
Register 2 Register 3
Bit Slip Bit Slip
Register 2 Register 3
Bit Slip Bit Slip
Register 2 Register 3
Bit Slip Bit Slip
Register 2 Register 3
D19
D9
D29
D19
D99
D89
D119
D99
D119
D109
D18
D8
D28
D18
D98
D18
D118
D98
D118
D108
D17
D7
D27
D17
D97
D87
D117
D97
D117
D107
D16
D6
D26
D16
D96
D86
D116
D96
D116
D106
One bit
Seven more
One more
One more
D15
D5
slipped
D25
D15 bits slipped D95
D85 bit slipped D115
D95
bit slipped D115
D125
D14
D4
D24
D14
D94
D84
D114
D94
D114
D124
D13
D3
D23
D13
D93
D83
D113
D93
D113
D123
D12
D2
D22
D12
D92
D82
D112
D92
D112
D102
D11
D1
D21
D11
D91
D81
D111
D91
D111
D101
D10
D0
D20
D10
D90
D80
D110
D90
D110
D100
Zero bits slipped.
Counter = 0
D10 is the upcoming
bit to be slipped.
One bit slipped.
Counter = 1
D21 is the upcoming
bit to be slipped.
Eight bits slipped.
Counter = 8
D98 is the upcoming
bit to be slipped.
Nine bits slipped.
Counter = 9
D119 is the upcoming
bit to be slipped.
10 bits slipped.
Counter = 0
Real data will resume
on the next byte.
Use the rx_channel_data_align signal within the device to activate
the data realigner. Designers can use internal logic or an external pin to
control the rx_channel_data_align signal. To ensure the rising edge
of the rx_channel_data_align signal is latched into the control logic,
the rx_channel_data_align signal should stay high for at least two
low-frequency clock cycles.
60
Preliminary
Altera Corporation