EP1SGX10C Datasheet, PDF (92/262 Pages) Altera Corporation – StratixGX FPGA Family

Stratix GX FPGA Family
Table 29. M-RAM Block Configurations (True Dual-Port)
Port A
64K × 9
32K × 18
16K × 36
8K × 72
64K × 9
v
v
v
v
Port B
32K × 18 16K × 36
v
v
v
v
v
v
v
v
8K × 72
v
v
v
v
The read and write operation of the memory is controlled by the WREN
signal, which sets the ports into either read or write modes. There is no
separate read enable (RE) signal.
Writing into RAM is controlled by both the WREN and byte enable
(byteena) signals for each port. The default value for the byteena
signal is high, in which case writing is controlled only by the WREN signal.
The byte enables are available for the ×18, ×36, and ×72 modes. In the
×144 simple dual-port mode, the two sets of byteena signals
(byteena_a and byteena_b) are combined to form the necessary
16 byte enables. Tables 30 and 31 summarize the byte selection.
Table 30. Byte Enable for M-RAM Blocks Notes (1), (2)
byteena[3..0]
[0] = 1
[1] = 1
[2] = 1
[3] = 1
[4] = 1
[5] = 1
[6] = 1
[7] = 1
datain ×18
[8..0]
[17..9]
–
–
–
–
–
–
datain ×36
[8..0]
[17..9]
[26..18]
[35..27]
–
–
–
–
datain ×72
[8..0]
[17..9]
[26..18]
[35..27]
[44..36]
[53..45]
[62..54]
[71..63]
92
Preliminary
Altera Corporation