EP1SGX10C Datasheet, PDF (55/262 Pages) Altera Corporation – StratixGX FPGA Family

Source-Synchronous Signaling with DPA
Figure 40. PLL & Channel Layout in EP1SGX40 Devices Notes (1), (2)
CLKIN
PLL (1)
1 Receiver
1 Transmitter
22 Rows
1 Transmitter
1 Receiver
INCLK0
INCLK1
1 Receiver
1 Transmitter
23 Rows
8
Fast
PLL 1
Fast
PLL 2
Eight-Phase
Clock
Eight-Phase
Clock
8
1 Transmitter
1 Receiver
CLKIN
PLL (1)
Notes to Figure 40:
(1) Corner PLLs do not support DPA.
(2) Not all eight phases are used by the receiver channel or transmitter channel in non-
DPA mode.
Altera Corporation
55
Preliminary