EP1SGX10C Datasheet, PDF (101/262 Pages) Altera Corporation – StratixGX FPGA Family

TriMatrix Memory
Independent Clock Mode
The memory blocks implement independent clock mode for true dual-
port memory. In this mode, a separate clock is available for each port
(ports A and B). Clock A controls all registers on the port A side, while
clock B controls all registers on the port B side. Each port, A and B, also
supports independent clock enables and asynchronous clear signals for
port A and B registers. Figure 67 shows a TriMatrix memory block in
independent clock mode.
Altera Corporation
101
Preliminary