EP1SGX10C Datasheet, PDF (165/262 Pages) Altera Corporation – StratixGX FPGA Family

I/O Structure
When using the IOE for DDR inputs, the two input registers clock double
rate input data on alternating edges. An input latch is also used within the
IOE for DDR input acquisition. The latch holds the data that is present
during the clock high times. This allows both bits of data to be
synchronous with the same clock edge (either rising or falling).
Figure 108 shows an IOE configured for DDR input. Figure 109 shows the
DDR input timing diagram.
Figure 108. Stratix GX IOE in DDR Input I/O Configuration Note (1)
Column or Row
Interconnect
ioe_clk[7..0] (1)
I/O Interconnect DQS Local
[15..0] (1) Bus (1), (2)
To DQS Local
Bus (3)
VCCIO
Optional
PCI Clamp
VCCIO
Programmable
Pull-Up
Resistor
sclr
clkin
Output Clock
Enable Delay
aclr/prn
Input Pin to
Input Register Delay
Input Register
D
Q
ENA
CLRN/PRN
Bus-Hold
Circuit
Chip-Wide Reset
Input Register
D
Q
ENA
CLRN/PRN
Latch
D
Q
ENA
CLRN/PRN
Notes to Figure 108:
(1) All input signals to the IOE can be inverted at the IOE.
(2) This signal connection is only allowed on dedicated DQ function pins.
(3) This signal is for dedicated DQS function pins only.
Altera Corporation
165
Preliminary